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IC89E54/58/64
8-BITS SINGLE MICROCONTROLLER with 16/32/64-Kbytes of FLASH, 256 byte +512 byte RAM
FEATURES
* 80C52 based architecture * 256 Byte RAM internal RAM and 512 Bytes auxiliary RAM available * Three 16-bit Timer/Counters * Full duplex serial channel * Boolean processor * Power Save Mode :
GENERAL DESCRIPTION
IC89E54, IC89E58, IC89E64 are members of ICSI embedded microcontroller family. The IC89E54/58/64 uses the same powerful instruction set, has the same architecture, and is pin-to-pin compatible with standard 80C51 controller devices. They have IC89E54/58/64 all functions and some enhanced function is included. These enhanced functions include 512 bytes auxiliary memory, 36 I/O pins (44 pin package only), 8 interrupts (44 pin package only) with twolevel priority, Power off flag, Low EMI mode, power down mode is waken up from interrupt level trigger mode.
1) Idle Mode
2) Power Down Mode - waken up from interrupt level trigger mode Program memory lock - Lock bits (3) Four 8-bit I/O ports, 32 I/O lines Memory addressing capability - 64K Program Memory and 64K Data Memory CMOS and TTL compatible Maximum speed ranges at Vcc = 5V is 40 MHz and most instructions execute in 0.3 s Packages available: - 40-pin DIP - 44-pin PLCC - 44-pin PQFP 16K/32K/64K Byte Flash Memory with fast-pulse programming algorithm 36 I/O pins(above 44-pin package only) 8 interrupts vectors (above 44-pin package only) Low EMI mode
* * * * * *
T2/P1.0 T2EX/P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST RxD/P3.0 TxD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 WR/P3.6 RD/P3.7 XTAL2 XTAL1 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
VCC P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA/VPP ALE/PROG PSEN P2.7/A15 P2.6/A14 P2.5/A13 P2.4/A12 P2.3/A11 P2.2/A10 P2.1/A9 P2.0/A8
*
* * *
Figure 1. IC89E54/58/64 Pin Configuration: 40-pin DIP
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. (c) Copyright 2000, Integrated Circuit Solution Inc.
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P1.1/T2EX
INT3/P4.2
P0.0/AD0
P0.1/AD1
P0.2/AD2
41
INDEX P1.5 P1.6 P1.7 RST RxD/P3.0 INT2/P4.3 TxD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 7 8 9 10 11 12 13 14 15 16 17
6
5
4
3
2
1
44
43
42
40 39 38 37 36 35 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA/VPP P4.1 ALE/PROG PSEN P2.7/A15 P2.6/A14 P2.5/A13
TOP VIEW
18
19
20
21
22
23
24
25
26
27
28
WR/P3.6
XTAL2
XTAL1
VSS
A8/P2.0
A9/P2.1
P4.0
A10/P2.2
A11/P2.3
Figure 2. IC89E54/58/64 Pin Configuration: 44-pin PLCC
2
A12/P2.4
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RD/P3.7
P0.3/AD3
34 33 32 31 30 29
P1.0/T2
VCC
P1.4
P1.3
P1.2
IC89E54/58/64
P1.1/T2EX
INT3/P4.2
P0.0/AD0
P0.1/AD1
P0.2/AD2
44 P1.5 P1.6 P1.7 RST RxD/P3.0 INT2/P4.3 TxD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 1 2 3 4 5 6 7 8 9 10 11 12
43
42
41
40
39
38
37
36
35
P0.3/AD3
P1.0/T2
P1.4
P1.3
P1.2
VCC
34 33 32 31 30 29 28 27 26 25 24 23 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA/VPP P4.1 ALE/PROG PSEN P2.7/A15 P2.6/A14 P2.5/A13
13
14
15
16
17
18
19
20
21
22
WR/P3.6
VSS
A8/P2.0
A9/P2.1
P4.0
A10/P2.2
A11/P2.3
Figure 3. IC89E54/58/64 Pin Configuration: 44-pin PQFP/LQFP
A12/P2.4
XTAL2
RD/P3.7
XTAL1
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16K/32K/64K MAIN CODE FLASH VCC
SFR BLOCK
256 BYTE RAM
512 BYTE AUX RAM
VSS
ALE PSEN PORT 2 CLOCK & TIMING RST EA XTAL2 XTAL1
P2[7:0]
80C32 CPU CORE
INT 2 INT 3
P0[7:0]
PORT 0
PORT 4
P4[3:0]
PORT 1
TIMER 2
UART
INT0 TIMER 0
INT1 TIMER 1
PORT 3
P1[7:0]
P3[7:0]
Figure 4. IC89E54/58/64 Block Diagram
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Table 1. Detailed Pin Description Symbol P0.0-P0.7 PDIP 39-32 PLCC 43-36 PQFP 37-30 I/O I/O Name and Function Port 0: Port 0 is an open-drain, bi-directional I/O port. Port 0 pins that have 1s written to them float and can be used as highimpedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application, it uses strong internal pullups when emitting 1s. Port 0 also receives the command and code bytes during memory program and verification, and outputs the code bytes during program verification. External pullups are required during program verification. Port 1: Port 1 is an 8-bit bi-directional I/O port with internal pullups. Port 1 pins that have 1s written to them are pulled high by the internal pullups and can be used as inputs. As inputs, port 1 pins that are externally pulled low will source current because of the internal pullups. Port 1 also receives the low-order address byte during memory program and verification. T2(P1.0) : Timer/counter 2 external count input. T2EX(P1.1): Timer/counter 2 trigger input. Port 2: Port 2 is an 8-bit bi-directional I/O port with internal pullups. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 2 pins that are externally pulled low will source current because of the internal pullups. Port 2 emits the high order address byte during fetches from external program memory and during accesses to external data memory that used 16-bit addresses. In this application, it uses strong internal pullups when emitting 1s. During accesses to external data memory that use 8-bit addresses, port 2 emits the contents of the P2 special function register. Port 2 also receives the high-order address bits from A13 to A8 and some control signals during Flash programming and verification. P2.6, P2.7 are the control signals while the chip programs and erases. P2.6 is a program command strobe signal. P2.7 is a data output enable signal.
P1.0-P1.7
1-8
2-9
40-44
I/O
1 2 P2.0-P2.7 21-28
2 3 24-31
40 41 18-25
I I I/O
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Table 1. Detailed Pin Description ( contnued) i Symbol P3.0-P3.7 PDIP 10-17 PLCC 11, 13-19 PQFP 5, 7-13 I/O I/O Name and Function Port 3: Port 3 is an 8-bit bi-directional I/O port with internal pullups. Port 3 pins that have 1s written to them are pulled high by the internal pullups and can be used as inputs. As inputs, port 3 pins that are externally pulled low will source current because of the internal pullups. Port 3 also serves the special features of the IC89E54/58/64, as listed below: 10 11 12 13 14 15 16 17 P4.0-P4.3 11 13 14 15 16 17 18 19 23 34 1 12 5 7 8 9 10 11 12 13 17 29 39 6 I O I I I I O O I/O RxD (P3.0): Serial input port. TxD (P3.1): Serial output port. INT0 (P3.2): External interrupt. Serve as A14 during memory program and verification. INT1 (P3.3): External interrupt. Serve as A15 during memory program and verification. T0 (P3.4): Timer 0 external input. T1 (P3.5): Timer 1 external input. WR (P3.6):External data memory write strobe. Control signal during memory program, verification and erase. RD (P3.7): External data memory read strobe. Control signal during memory program, verification and erase. Port 4: In mode 0, Port 4 is an 8-bit bi-directional I/O port with internal pullups. Port 4 pins that have 1s written to them are pulled high by the internal pullups and can be used as inputs. As inputs, port 4 pins that are externally pulled low will source current because of the internal pullups. In mode 1, 2, 3, Port 4 is an address strobe signal which appears with RD or WR signals. Port 4 also serves the special features, as listed below: INT2 (P4.3): External interrupt INT3 (P4.2): External interrupt Reset: A high on this pin for two machine cycles while the oscillator is running resets the device. An internal resistor to VSS permits a power-on reset using only an external capacitor. A small internal resistor permits power-on reset using only a capacitor connected to VCC. RST is an input control signal during memory program and verification. Crystal 2: Output from the inverting oscillator amplifier. Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits.
12 1 RST 9 10
6 39 4 I
XTAL 2 XTAL 1
18 19
20 21
14 15
O I
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Table 1. Detailed Pin Description ( contnued) i Symbol PSEN PDIP 29 PLCC 32 PQFP 26 I/O O Name and Function Program Store Enable: The read strobe to external program memory. When the device is executing code from the external program memory, PSEN is activated twice each machine cycle except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. PSEN is an input control signal while memory program and verification. Address Latch Enable: Output pulse for latching the low byte of the address during an address to the external memory. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. This pin is also the program pulse input (PROG) during programmable memory programming and erase. EA/VPP 31 35 29 I External access enable: EA must be externally held low to enable the device to fetch code from external program memory locations 0000H to FFFFH. If EA is held high, the device executes from internal program memory unless the program counter contains an address grater than 3FFFH/7FFFH respecting to IC89C54/58 and the device always executes internal program memory in IC89C64. This is also receives the 12 V programming enable voltage (Vpp) during Flash programming, when 12 V programming is selected. Ground: 0V reference. I Power Supply: This is the power supply voltage for operation.
ALE/PROG
30
33
27
I/O
Vss Vcc
20 40
22 44
16 38
OPERATING DESCRIPTION
The detail description of the IC89E54/58/64 included in this description are: * Memory Map and Registers * Timer/Counters * Serial Interface * Interrupt System * Other Information * Flash Memory
MEMORY MAP AND REGISTERS Program Memory and data memory
Table 2 shows program memory and data memory size versus three products. The IC89E54/58/64 series includes a standard IC80C32 and a 16K/32K/64K Flash Memory. The IC89E54/58/64 includes IC80C32, a 16K/32K/64K Flash and some enhanced functions. The figures 3~5 show IC89E54/58/64 program memory architecture and program memory access status versus EA pin. These enhanced functions are described in later descriptions. The program memory and data memory access ranges are listed table 1. The AUX RAM status is disable after reset, so MOVX instructions will access external RAM. If set ENARAM bit, the AUX RAM will be enabled and MOVX instructions will access AUX RAM in 0000H~01FFH, access external RAM in 0200H~FFFFH. Figure 6 shows the external data memory and AUX RAM accesses relation. 7
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Table 2. Program memory and Data memory sizes Main Flash IC89E54 IC89E58 IC89E64 16K Bytes : [0H~3FFFH] 32K Bytes : [0H~7FFFH] 64K Bytes : [0H~FFFFH] RAM Size 256 Bytes : [ 0-FFH] 256 Bytes : [ 0-FFH] 256 Bytes : [ 0-FFH] AUX RAM Size 512 Bytes : [ 0-1FFH] 512 Bytes : [ 0-1FFH] 512 Bytes : [ 0-1FFH]
FFFFH
FFFFH
External Range External Range
4000H 3FFFH Internal Range 0000H 0000H
EA = 0
EA = 1
Figure 5. IC89E54 Flash Architecture
FFFFH
FFFFH
External Range
8000H 7FFFH
External Range
Internal Range
0000H
0000H
EA = 0
EA = 1
Figure 6. IC89E58 Flash Architecture 8 I egr ed C i cui nt at r tSol i I uton nc.
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FFFFH Internal Range (Block 2) F000H EFFFH
FFFFH
External Range
Internal Range (Block 1)
0000H
0000H
EA = 0
EA = 1
Figure 7. IC89E64 Flash Architecture
EXTRAM = 0 FFFFH
EXTRAM = 1 FFFFH
FFH Indirect RAM 80H 7FH Direct/Indirect RAM 00H
FFH SFR 80H
External Range
External RAM
0000H 0200H 01FFH Auxiliary Internal RAM 0000H
Figure 8. IC89E54/58/64 Data Memory Architecture
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F8H F0H E8H E0H D8H D0H C8H C0H B8H B0H A8H A0H 98H 90H 88H 80H ACC 00000000 P4[3:0] XXXX1111 PSW 00000000 T2CON 00000000 XICON 00000000 IP XX000000 P3 11111111 IE 0X000000 P2 11111111 SCON 00000000 P1 11111111 TCON 00000000 P0 11111111 B 00000000
FFH F7H EFH E7H DFH D7H RCAP2L 00000000 P4CONA 00000000 RCAP2H 00000000 P4CCONB 00000000 TL2 00000000 TH2 00000000 CFH C7H BFH P43AL 00000000 P42AL 00000000 PH43AH 00000000 P42AH 00000000 P2ECON 0000XX00 B7H AFH A7H SBUF XXXXXXXX P41AL 00000000 TMOD 00000000 SP 00000000 TL0 00000000 DPL 00000000 TL1 00000000 DPH 00000000 TH0 00000000 P40AL 00000000 P41AH 00000000 TH1 00000000 P40AH 00000000 AUXR XXX00000 PCON 0XX00000 P2EAL 00000000 P2EAH 00000000 9FH 97H 8FH 87H
Figure 9. IC89E54/58/64 SFRs Map and Reset value (The gray blocks are non-standard.) These descriptions are added from standard IC80C32. So, more information for SFRs and memory refer to IC80C32.
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The timers/counters
Refer to IC80C32 data sheet.
The serial interface
Refer to IC80C32 data sheet.
The interrupt system
There are 8 interrupt vectors in 44 pins package and 6 interrupt vectors in 40 pins package. Eight interrupt vectors only exist in IC89E54/58/64 series. INT2 and INT3 are new interrupts that add on standard IC80C32. The interrupt information shows in Table 3. The interrupt architecture shows in figure 10. External interrupt 2 and 3 control register is XICON shown in following. Two additional external interrupts, INT2 and INT3, whose function are similar to those of external interrupt 0 and 1 in the standard 80C32. The functions/status of these interrupts are determined/shown by the bits in the XICON(External Interrupt Control) register. The XICON register is bit-addressable but is not a standard register in the 80C32. Its address is at 0C0H. To set/clear bits in the XICON register, one can use the "SETB (/CLR) bit" instruction. Table 3. Eight interrupt information Interrupt Source External Interrupt 0 Timer/Counter 0 External Interrupt 1 Timer/Counter 1 Serial Port Timer/Counter 2 External Interrupt 2
(1)
Vector Address 03H 0BH 13H 1BH 23H 2BH 33H 3BH
Polling Sequence within priority leve 0 (Highest) 1 2 3 4 5 6 7 (Lowest)
Enable Required Settings IE.0 IE.1 IE.2 IE.3 IE.4 IE.5 XICON.2 XICON.6
Interrupt Type Edge/Level TCON.0 TCON.2 XICON.0 XICON.3
External Interrupt 3 (1) Note:
1. Interrupt 2 and interrupt 3 exist in IC89E54/58/64 44 pins package.
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XICON(C0H)
B7 Flag Name Bit 7 6 5 4 3 2 1 0 PX3 B6 EX3 B5 IE3 B4 IT3 B3 PX2 Description External interrupt 3 priority high if set. External interrupt 3 enable if set. If IT3=1, IE3 is set/cleared automatically by hardware when interrupt is detected/serviced. External interrupt 3 is falling-edge/low-level triggered when this bit is set/cleared by software. External interrupt 2 priority high if set. External interrupt 2 enable if set. If IT2=1, IE2 is set/cleared automatically by hardware when interrupt is detected/serviced. External interrupt 2 is falling-edge/low-level triggered when this bit is set/cleared by software. B2 EX2 B1 IE2 B0 IT2
Name PX3 EX3 IE3 IT3 PX2 EX2 IE2 IT2
EA
INT0
IT0
IE0
EX0
PX0
TF0
ET0
PT0
IE1 INT1
IT1
EX1
PX1
TF1
ET1
PT1
RI/TI
ES
PS
TF2/EXF2
ET2
PT2
INT2
XICON.0
XICON.2
EX2
IT2
INT3
XICON.3
XICON.6
EX3
IT3
Figure 10. IC89E54/58/64 Interrupt Architecture
These descriptions are added from standard 80C32. So, more detailed information for interrupts refer to IC80C52. 12 I egr ed C i cui nt at r tSol i I uton nc.
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Operation of Power-Save Mode
Refer to IC80C32 data sheet.
Instruction Definitions
Refer to IC80C32 data sheet.
Enhanced Function Port 4
Port 4, SFR P4 at address D8H, is a 4-bit multipurpose programmable I/O port. Each bit can be configured individually by software. The Port 4 has four different operation modes. In mode 0, P4.0~P4.3 is a bi-directional I/O port which is same as port 1. P4.2 and P4.3 also serve as external interrupt INT3 and INT2 if enabled. In mode 1, P4.0~P4.3 are read data strobe signals which are synchronized with beginning of read address signal at specified address. These signals can be used as chip-select signals for external peripherals. In mode 2, P4.0~P4.3 are write data strobe signals which are synchronized with beginning of written address signal at specified address. These signals can be used as chip-select signals for external peripherals. In mode 3, P4.0~P4.3 are write data strobe signals which are synchronized with beginning of read or written address signal at specified address. These signals can be used as chip-select signals for external peripherals. When Port 4 is configured with the feature of chip-select signals, the chip-select signal address range depends on the contents of the SFRs P4xAH, P4xAL, P4CONA an P4CONB. The registers P4xAH and P4xAL contain the 16-bit base address of P4.x. The registers P4CONA and P4CONB contain the control bits to configure the Port 4 operating mode. Here is an example to program the P4.0 as a write strobe signal at the I/O port address 1234H~1237H and positive polarity, and P4.1~P4.3 are used as general I/O ports. MOV MOV MOV MOV MOV P40AH,#12H P40AL,#34H P4CONA,#00001010B P4CONB,#00H P2ECON,#10H ;Define the base I/O address 1234H for P4.0 as an special function pin. ;Define the P4.0 as a write strobe signal pin and the compartor, length is 14. ;P4.1~P4.3 as general I/O port which are the same as Port 1. ;Write the P40SINV=1 to inverse the P4.0 write strobe polarity, default is ;negative.
Then any instruction MOVX @DPTR,A (with DPTR=1234H~1237H) will generate the positive polarity write strobe signal at pin P4.0. And the instruction MOV P4,#XX will output the bit 3 to bit 1 of data #XX to pin P4.3~P4.1. The SFRs of Port 4 are described in following. Figure 11 shows architecture of Port 4. Port 4 base Address Registers : Reset values are 00000000B. P40AH, P40AL(85H, 84H): The Base address register for comparator of P4.0. P40AH contains the high-order byte of address, P40AL contains the low-order byte of address. P41AH, P41AL(95H, 94H): The Base address register for comparator of P4.1. P41AH contains the high-order byte of address, P41AL contains the low-order byte of address. P42AH, P42AL(ADH, ACH): The Base address register for comparator of P4.2. P42AH contains the high-order byte of address, P42AL contains the low-order byte of address. P43AH, P43AL(B5H , B4H): The Base address register for comparator of P4.3. P43AH contains the high-order byte of address, P43AL contains the low-order byte of address.
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P4CONB (C3H)
B7 Flag Name Bit 7,6 P43FUN1 B6 P43FUN0 B5 P43CMP1 B4 P43CMP0 B3 P42FUN1 Description =00: Mode 0. P4.3 is a general purpose I/O port which is the same as Port 1. =01: Mode 1. P4.3 is a Read Strobe Signal for chip selecting purpose. The address range depends on the SFRs P43AH, P43AL and flags P43CMP1, P43CMP0. =10: Mode 2. P4.3 is a Write Strobe Signal for chip selecting purpose. The address range depends on the SFRs P43AH, P43AL and flags P43CMP1, P43CMP0. =11: Mode 3. P4.3 is a Read/Write Strobe Signal for chip selecting purpose. The address range depends on the SFRs P43AH, P43AL and flags P43CMP1, P43CMP0. Chip-select signals for address comparison. =00: Compare the full address (16 bits length) with the base address register P43AH, P43AL. =01: Compare the 15 high bits (A15-A1) of address bus with the base address register P43AH, P43AL. =10: Compare the 14 high bits (A15-A2) of address bus with the base address register P43AH, P43AL. =01: Compare the 8 high bits (A15-A8) of address bus with the base address register P43AH, P43AL. The P4.2 function control bits which are the similar definition as P42FUN1, P42FUN0. The P4.2 address comparator length control bits which are the similar definition as P42CMP1, P42CMP0. B2 P42FUN0 B1 B0 P42CMP1 P42CMP0
Name P43FUN1 P43FUN0
5.4
P43CMP1 P43CMP0
3,2 1,0
P42FUN1 P42FUN0 P42CMP1 P42CMP0
P4CONA (C2H)
B7 Flag Name Bit 7,6 5,4 3,2 1,0 P41FUN1 B6 P41FUN0 B5 P41CMP1 B4 B3 B2 P40FUN0 B1 P40CMP1 B0 P40CMP0 P41CMP0 P40FUN1 Description The P4.1 function control bits which are the similar definition as P41FUN1, P41FUN0. The P4.1 address comparator length control bits which are the similar definition as P41CMP1, P41CMP0. The P4.0 function control bits which are the similar definition as P40FUN1, P40FUN0. The P4.0 address comparator length control bits which are the similar definition as P40CMP1, P40CMP0.
Name P41FUN1 P41FUN0 P41CMP1 P41CMP0 P40FUN1 P40FUN0 P40CMP1 P40CMP0
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P4(D8H) :
B7 Flag Name Bit 7-4 3 2 1 0 Name P4.3 P4.2 P4.1 P4.0 These bits are reserved. Port 4 Data bit that output to pin P4.3 at mode 0. Port 4 Data bit that output to pin P4.2 at mode 0. Port 4 Data bit that output to pin P4.1 at mode 0. Port 4 Data bit that output to pin P4.0 at mode 0. B6 B5 B4 B3 P4.3 Description B2 P4.2 B1 P4.1 B0 P4.0
P4xCSINV P4.x DATA OUTPUT
RD_CS
WR_CS
PIN P4.x
WRITE ENABLE READ ENABLE
RD/WR_CS
P4xFUN0 ADDRESS BUS P4xFUN1
P4xAL P4xAH
P4xCMP0 P4xCMP1
INPUT SIGNAL
Figure 11. IC89E54/58/64 Port 4 Architecture
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P2ECON(AEH)
B7 Flag Name P43CSINV Bit 7 Name P43CSINV B6 P42CSINV B5 P41CSINV B4 P40CSINV Description The active polarity of P4.3 when pin P4.3 is defined as read/write strobe signal. =1: P4.3 is active high when pin P4.3 is defined as read/write strobe signal. =0: P4.3 is active low when pin P4.3 is defined as read/write strobe signal. 6 5 4 3,2 1,0 P42CSINV P41CSINV P40CSINV P2CN1, P2CN0 The similarity definition as P43SINV. The similarity definition as P43SINV. The similarity definition as P43SINV. Reserve =00 : Pin P2.7-P2.0 is the standard 8052 port 2. =01 : Pins P2.7-P2.0 is input buffer port which the port enable address depends on the content of P2EAL and P2EAH. =10 : Pins P2.7-P2.0 is output-latched port which the port enable address depends on the content of P2EAL and P2EAH. =11 : Undefined. B3 B2 B1 P2CN1 B0 P2CN0
PORT 2 OUTPUT DATA BUS MUX INTERNAL DATA BUS 74373 WRITE
P2CN1
PORT 2
16-BIT COMPARATOR
ADDRESS BUS
P2CN0
P2EAL P2EAH
74244
DEMUX READ PORT 2 INPUT DATA BUS
Figure 12. IC89E54/58/64 Port 2 Architecture 16 I egr ed C i cui nt at r tSol i I uton nc.
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P2EAH, P2EAL: The Port Enable Address Registers for Port 2 is defined as input buffer like 74244, or an output-latched logic like a 74373. The P2EAH contains the high-order byte of address, the P2EAL contains the low-order byte of address. Figure 12 shows architecture of Port 2. The following example shows how to program the Port 2 as a output-latched port at address 5678H. MOV P2EAL,#78H ;High-order byte of address to enable Port 2 latch function. MOV P2EAH,#56H ;Low-order byte of address to enable Port 2 latch function. MOV P2ECON,#02H ;Configure the port 2 as an output-latched port. MOV DPTR,#5678H ;Move data 5678H to DPTR. MOV A,#55H MOVX @DPTR,A ;The pins P2.7~P2.0 will output and latch the value 55H. When Port 2 is configured as 74244 or 74373 function, the instruction "MOV P2,#XX" will write the data #XX to P2 register only but not output to port pins P2.7~P2.0. Power Down Mode When the PD bit in the PCON register is set, the processor enters the power-down mode. In this mode, all of the clocks are stopped, including the oscillator. To exit from power-down mode is by a hardware reset or external interrupts INT0 to INT3 when enabled and set to level triggered. To ensure that the oscillator is stable before the CPU restarts, the IC89E54/ 58/64 series provide adjustable internal software delay counter. By the default, the device will experience a delay of 2048 clock cycles while the oscillation is recognized. The period of delay is selected by configuring the AUXR register bits OD0, OD1 and OD2. Reduce EMI Emission Because of on-chip flash, when a program is running in internal program memory space, the ALE will be unused. The transition of ALE will cause larger noise and EMI effect, so it can be turned off to reduce noise and EMI emission if it is useless. Turning off the ALE signal transition only requires setting the bit 0 of the AUXR SFR, which is located at 08EH. When ALE is turned off, it will be reactivated when the program accesses external ROM/RAM data or jumps to execute an external ROM code. The ALE signal will turn off again after it has been completely accessed or program returns to internal ROM code space. The ALED bit in the AUXR register, when set, disables the ALE output.
AUXR(8EH) : Reset value is xxx0x000B.
Flag Name Bit 7-5 4 3 2-1 Name ENARAM OD1-OD0 These bits are reserved. 1, Enable AUX RAM. These bits are reserved. Select the delay periods of oscillation when waking up from power-down mode. OD1 OD0 0 0 1 1 0 ALED 0 1 0 1 Delay Period 2,048 clock cycles (Default) 8,192 clock cycles 32,768clock cycles 131,072 clock cycles B7 B6 B5 B4 ENARAM B3 Description B2 OD1 B1 OD0 B0 ALED
1, Turn off ALE output while CPU accesses internal Flash memory. 17
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Power Control Register PCON(87H) :
B7 Flag Name Bit 7 6-4 3 2 1 0 Name SMOD GF1 GF0 PD IDL SMOD B6 B5 B4 B3 GF1 Description Double baud rate bit. If Timer 1 is used to generate baud rate and SMOD=1, the baud rate is doubled when the serial port is used in modes 1, 2, or 3. These bits are reserved. General purpose flag bit. General purpose flag bit. Power down bit. Setting this bit activates power down operation in the IC89E54/58/64. Idle mode bit. Setting this bit activate idle mode operation in the 89E54/58/64. If 1s are written to PD and IDL at the same time, PD takes precedence. B2 GF0 B1 PD B0 IDL
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FLASH MEMORY PROGRAMMING
The Flash architecture of IC89E54/58/64 is shown in Figure 13. IC89E54/58 include block 1 and lock bits block. The signature bytes are fixed value reside in MCU, they are read only. Block 2 resides in IC89E64 only.
0030H 0032H
3x8 bits Signature Bytes
0030H 0032H
3x8 bits Signature Bytes
0030H 0032H
3x8 bits Signature Bytes
0000H 16K Flash ( Block 1) 3FFFH
0000H
0000H
32K Flash ( Block 1) 60K Flash ( Block 1)
7FFFH Dummy Address
Dummy Address EFFFH F000H FFFFH
4K Flash ( Block 2)
3 Lock Bits Flash Cell
3 Lock Bits Flash Cell
3 Lock Bits Flash Cell
IC89E54
IC89E58
IC89E64
Figure 13. The Flash Architecture of IC89E54/58/64
EXTERNAL HOST MODE
The IC89E54/58/64 provide the user with a direct flash memory access that can be used for programming into the flash memory without using the CPU. The direct flash memory access is entered using the External Host Mode. While the reset input (RST) is continually held active (high), if the PSEN pin is forced by an input with low state, the device enters the External Host Mode arming state at this time. The CPU core is stopped from running and all the chip I/O pins are reassigned and become flash memory access and control pins. At this time, the external host should initiate a "Read Signature Bytes" operation. After the completion of the "Read Signature Bytes" operation, the device is armed and enters the External Host Mode. After the device enters into the External Host Mode, the internal flash memory blocks are accessed through the reassigned I/O port pins by an external host, such as a printed circuit board tester, a PC controlled development board or an MCU programmer.
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IC89E54/58/64
When the chip is in the external host mode, Port 0 pins are assigned to be the parallel data input and output pins. Port 1 pins are assigned to be the low order address bus signals for the internal flash memory (A0-A7). The first six bits of Port 2 pins (P2[0:5]) are assigned to be the upper order address bus signals for the internal flash memory (A8-A13) along with two of the Port 3 pins (P3.2 as A14 and P3.3 as A15). Two upper order Port 2 pins (P2.6 and P2.7) and two upper order Port 3 pins (P3.6 and P3.7) along with RST, PSEN, PROG/ALE, EA pins are assigned as the control signal pins. The P3. 4 is assigned to be the ready/busy status signal, which can be used for handshaking with the external host during a flash memory programming operation. The flash memory programming operation (Erase, Program, Verify, etc.) is internally selftimed and can be controlled by an external host asynchronously or synchronously. The insertion of an "arming" command prior to entering the External Host Mode by utilizing the "Read Signature Bytes" operation provides additional protection for inadvertent writes to the internal flash memory cause by a noisy or unstable system environment during the power-up or power unstable conditions. The External Host Mode uses hardware setup mode, which are decoded from the control signal pins, to facilitate the internal flash memory erase, test and programming process. The External Host Mode Commands are enabled on the falling edge of ALE/PROG. The list in Table 4 outlines all the setup conditions of normal mode. Before entering these written modes must have read 3 signature bytes.
Programming Interface
Some conditions must be satisfied before entering the programming mode. The conditions are listed in Table 4. The interface-controlled signals are matched these conditions, then the IC89E54/58/64 will enter received command mode. The flash command is accepted by the flash command decoder in command received mode. The programming interface is listed in figure 14.
VCC A7-A0 P1
VCC
A13-A8
P2.5-2.0
A15-A14
P3.3-3.2
IC89E54/58/64
10K
P0
D7-D0
H L PROG pulse 12V/H
RST PSEN ALE/PROG EA/VPP VSS
P3.4 P2.6 P2.7 P3.6 P3.7
Ready/Busy P2.6 P2.7 P3.6 P3.7
Figure 14. IC89E52/54/64 External Host Programming Signals 20 I egr ed C i cui nt at r tSol i I uton nc.
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Table 4. Flash Programming Mode Mode(1) Read Signature Byte Chip Erase Block 1 (2) Erase Block 2 (2) Erase Program Main code Program Lock Bit 1 Program Lock Bit 2 Program Lock Bit 3 Verify Lock Bits Verify Main Code RST H H H H H H H H H H PSEN L L L L L L L L L L PROG H EA H 12V/H 12V/H 12V/H 12V/H 12V/H 12V/H 12V/H H H P2.6 L H L L L H H H H L P2.7 L L H L H H H L L L P3.6 L L L H H H L H L H P3.7 P0[7:0] P1[7:0] P3[3:2] L L L L H H L L H H DO X X X DI X X X DO[3:1] DO AL X X X AL X X X X AL COM
H H
P2[5:0] HEX(3) AH 0 X 1 X 2 X 4 AH E X F X 3 X 5 X 9 AH C
1. To read the signature bytes 30H, 31H, 32H are needed before any written command. To read signature bytes is needed after any new mode changed. This operation provides additional protection for inadvertent writes to the internal flash memory cause by a noisy or unstable system environment during the power-up or unstable power condition. If any unstable power condition has happened while written operation proceeds, to read signature bytes again will re-enable written command. (Power-on reset voltage is about 2.7V.) 2. Block 1 includes flash address from 0000H to 3FFFH in IC89E54, from 0000H to 7FFFH in IC89E58, from 0000H to EFFFH in IC89E64. Block 2 includes F000H to FFFFH. Block 2 is resident in IC89E64 only. 3. "COM HEX" presents the combination value of [P3.7, P3.6, P2.7, P2.6].
Product Identification
The "Read Signature Bytes" command accesses the Signature Bytes that identify the device as IC89E54/58/64 and the manufacturer code. External programmers primarily use these Signature Bytes, shown in Table 4, in the selection of programming algorithms. The Read Signature Bytes command is selected by the byte code of 00h on P3[7:6] and P2[7: 6]. Manufacturer code of ICSI is "D5H" that reside in address 30H of signature. The flash memory sizes of MCU are shown in address 31H, code value 04H respect to 16K main flash memory, code value 08H respect to 32K main flash memory, code value 10H respect to 64K main flash memory. The address 32H value of signature byte respect to written operation VPP value, code value FFH respects to 12V and 55H respects to 5V. Table 5. Signature Bytes Information Addr 30H IC89E54 (VPP=12V) IC89E54 (VPP=5V) IC89E58 (VPP=12V) IC89E58 (VPP=5V) IC89E64 (VPP=12V) IC89E64 (VPP=5V) D5H D5H D5H D5H D5H D5H Addr 31H 04H 04H 08H 08H 10H 10H Addr 32H FFH 05H FFH 05H FFH 05H
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Arming Command
An arming command must take place before a Written Mode will be recognized by the IC89E54/58/64. This is to prevent accidental triggering of written operation due to noise or programmer error. The arming command is as follows: A Read Signature Bytes command is issued. This is actually a natural step for the programmer, but will also serve as the arming command. After the above sequence, all other Written Mode commands are enabled. Before the Read Signature Bytes command is received, all other Written Mode commands received are ignored. The IC89E54/8/64 will exit Written Mode if power off, so arming command is needed every power on for entering External Host Command Mode.
External Host Mode Commands
The following is a brief description of the commands. See Table 4 for all signal logic assignments for the External Host Mode Commands. The critical timing for all Erase and Program commands, is self-generated by the flash memory controller on-chip. The high-to-low transition of the PROG signal initiates the Erase and Program commands, which are synchronized internally. All the data in the memory array will be erased to FFH. Memory addresses that are to be programmed must be in the erased state prior to programming. Selection of the Erase command to use, prior to programming the device, will be dependent upon the contents already in the array and the desired programming field block. The "Chip Erase" command erases all bytes in both memory blocks of the IC89E54/58/64.This command ignores the "Lock bits" status and will erase the Security Byte. The "Chip Erase" command is selected by the byte code of 01H on P3 [7:6] and P2[7:6].
Flash Operation Status Detection (Ext. Host Handshake)
The IC89E54/58/64 provide two signals mean for an external host to detect the completion of a flash memory operation, therefore the external host can optimize the system Program or Erase cycle of the embedded flash memory. The end of a flash memory operation cycle (Erase or Program) can be detected by monitoring the Ready/Busy bit at Port 3.4. The following two Program commands are for programming new data into the memory array. Selection of which Program command to use for programming will be dependent upon the desired programming field size. The Program commands will not enable if the Lock bit 2 or Lock Bit 3 is enabled on the selected memory block. The "Program Main Code" command program data into a single byte. Ports P0[0:7] are used for data in. The memory location is selected by P1[0:7], P2[0:5], and P3[2:3] (A0-A15). The "Program Main Code" command is selected by the byte code on P3[6:7] and P2[6:7]. The "Verify Main Code" command allows the user to verify that the IC89E54/58/64 correctly performed an Erase or Program command. Ports P0[0:7] are used for data out. The memory location is selected by P1[0:7], P2[0:5], and P3[2:3] (A0-A15). These commands will not enable if any lock bit is enabled on the selected memory block.
Ready/Busy Busy
The progress of the flash memory programming can be monitored by the Ready/Busy output signal. The Ready/Busy indicates whether an Embedded Algorithm in Written State Machine (WSM) is in progress or complete. The RY/BY status is valid after the falling edge of the programming or erase controlled signal. If the output is low (Busy), the device is in an erasing/programming state with an internal verification. If the output is high, the device is ready to read data. If Ready/Busy signal doesn't generate a low pulse or doesn't return from low to high in an expected time, the programming/erasing action will be failed.
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Programming a IC89E54/58/64
To program new data into the memory array, supply 5 volts to VDD and RST, and perform the following steps. 1. Set RST to high and PSEN to low. 2. Read the "Read Signature Bytes" command to ensure the correct programming algorithm. 3. Raise EA High (either 12V or 5V). 4. Verify that the memory blocks for programming are in the erased state, FFH. If they are not erased, then erase them using the Chip Erase command. (Chip Erase operation will have a Ready/Busy signal output from P3.4, if Ready/Busy signal doesn't return from low to high in 7.2 sec, the Chip Erase operation will be failed.) 5. Set P2.6, P2.7, P3.6, P3.7 to a properly programming combination. 6. Select the memory location using the address lines (P1[0:7], P2[0:5], P3[2:3]). 7. Present the data in on P0[0:7]. 8. Pulse ALE/PROG. 9. Wait for low to high transition on Ready/Busy(P3.4). If Ready/Busy is from low to high, this address is programmed completely. If Ready/Busy pin don't return from low to high in 720us while programming one byte, the Programming operation will be failed. 10. Repeat steps 6~9 until programming is finished.
Lock bits Features
The IC89E54/58/64 provide three lock bits to protect the embedded program against software piracy. These three bytes are user programmable. The relation between lock bits status and protection type are listed in table 6. Table 6. Lock Bits Features Program Lock bits LB1 1 2 U P LB2 U U LB3 U U No program lock feature enabled. MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory, EA is sampled and latched on reset, and Data verification is disabled. ("Verify Signature Byte" and "Verify Lock Bits are still enabled.) 3 4 P P P P U P Same as 2, also further written operation of the Flash is disabled Same as 3, also external execution is disabled. Protection in Normal Mode
Special Issue
There are two conditions must be sure. One is P2.6 and P2.7 can not be low levels when RST pin falling edge. Another is P4.3 can not be low level while RST falling edge. One of upper case is generate, the program will not be executing correctly.
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ABSOLUTE MAXIMUM RATINGS
Parameter Operating Temperature Under Bias Storage Temperature Range Voltage on any other pin to Vss Power Dissipation (Based on package heat transfer limitations, not device power consumption)
Note: 1. Operating temperature is for commercial products defined by this specification. 2. Minimum DC input voltage is -0.5V. During transitions, inputs may undershoot to -2. 0V for periods less than 20 ns. Maximum DC voltage on output pins is Vcc + 0.5V which may overshoot to Vcc + 2.0V for periods less than 20 ns.
Rating 0 to +70 -65 to +125 -2.0 to +7.0 1.5
Unit C(1) C V(2) W
OPERATING RANGE(1)
Range Commercial Ambient Temperature 0C to +70C VCC +4.5V to +5V Oscillator Frequency 3.5 to 40 MHz
Note: 1. Operating ranges define those limits between which the functionality of the device is guaranteed.
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DC CHARACTERISTICS
( Ta = 0C to 70C; VCC = 5V+10% ; VSS = 0V ) Symbol VIL VIL1 VIH VIH1 VSCH+ VSCH- VOL(1) Parameter Input low voltage Input low voltage (XTAL1, EA) Input high voltage (except XTAL 1, RST, EA) Input high voltage (XTAL 1, EA) RST positive schmitt-trigger threshold voltage RST negative schmitt-trigger threshold voltage Output low voltage (Ports 1, 2, 3) VOL1(1) Output low voltage (Port 0, ALE, PSEN) VOH Output high voltage (Ports 1, 2, 3, ALE, PSEN) Iol = 100 A IOL = 1.6 mA IOL = 3.5 mA IOL = 200 A IOL = 3.2 mA IOL = 7.0 mA IOH = -10 A Vcc = 4.5V ~ 5.5V IOL = -25 A IOL = -60 A VOH1 Output high voltage (Port 0, ALE, PSEN) IOH = -80 A Vcc = 4.5V ~ 5.5V IOH = -300 A IOH = -800 A IIL ILI ITL RRST Note:
1. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 10 mA Maximum IOL per 8-bit port Port 0: 26 mA Ports 1, 2, 3: 15 mA Maximum total IOL for all output pins: 71 mA If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink greater than the listed test conditions.
Test conditions
Min -0.5 -0.5 0.2Vcc + 0.9 0.7Vcc 0.7Vcc 0 -- -- -- -- -- -- 0.9Vcc 0.75Vcc 2.4 0.9Vcc 0.75Vcc 2.4 -- -10 -- 50
Max 0.2Vcc - 0.1 0.2Vcc - 0.3 Vcc + 0.5 Vcc + 0.5 Vcc + 0.5 0.3Vcc 0.3 0.45 1.0 0.3 0.45 1.0 -- -- -- -- -- -- -50 +10 -650 300
Unit V V V V V V V V V V V V V V V V V V A A A K
Logical 0 input current (Ports 1, 2, 3) VIN = 0.45V Input leakage current (Port 0) Logical 1-to-0 transition current (Ports 1, 2, 3) RST pulldown resister VIN = 0.45V or Vcc VIN = 2.0V VIN = 0V
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IC89E54/58/64
POWER SUPPLY CHARACTERISTICS
Symbol Icc Parameter Power supply current Active mode
(1)
Test conditions Vcc=5.0V 12 MHz 16 MHz 20 MHz 24 MHz 32 MHz 40 MHz
Min -- -- -- -- -- -- -- -- -- -- -- -- --
Max 20 26 32 38 50 62 5 6 7.6 9 12 15 50
Unit mA mA mA mA mA mA mA mA mA mA mA mA A
Idle mode
12 MHz 16 MHz 20 MHz 24 MHz 32 MHz 40 MHz
Power-down mode
Vcc=5.0V
Note: 1. The ICC test conditions are shown below. Minimum VCC for Power Down is 2 V.
Vcc Vcc RST Vcc Vcc P0
P0
Vcc Icc RST Vcc Vcc
Icc
NC CLOCK SIGNAL
XTAL2 XTAL1 GND
NC CLOCK SIGNAL
XTAL2 XTAL1 GND
EA
EA
Figure 15. Active Mode
Vcc Icc RST Vcc Vcc P0
Figure 16. Idle Mode
NC
XTAL2 XTAL1 GND
EA
Figure 17. Power Mode (VCC=2.0V~6.0V) 26 I egr ed C i cui nt at r tSol i I uton nc.
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tCLCX
Vcc -- 0.5V 0.45V
0.7Vcc 0.2Vcc -- 0.1
tCHCX
tCHCL tCLCL
tCLCH
Figure 18. Clock Singal Waveform for Icc Tests in Active and Idle Mode (tCLCH=tCHCL=5 ns)
AC CHARACTERISTICS
(Ta=0Cto 70C; VCC=5V 10%; VSS=0V; C1 for port 0, ALE and PSEN Outputs=100pF; C1 for other outputs=80pF)
EXTERNAL MEMORY CHARACTERISTICS
24 MHz Clock Min Max -- -- 68 -- 26 -- 31 -- -- 147 31 -- 110 -- -- 105 0 -- -- 37 -- 188 -- 10 230 -- 230 -- -- 157 0 -- -- 78 -- 282 -- 323 105 145 146 -- 26 -- 31 -- -- 0 26 57 40 MHz Clock Min Max ---- 35 -- 10 -- 15 -- -- 80 15 -- 60 -- -- 55 0 -- -- 20 -- 105 -- 10 130 -- 130 -- -- 90 0 -- -- 45 -- 165 -- 190 55 95 80 -- 10 -- 15 -- -- 0 10 40 Variable Oscillator (3.5 - 40 MHz) Min Max 3.5 40 2tCLCL-15 -- tCLCL-15 -- tCLCL-10 -- -- 4tCLCL-20 tCLCL-10 -- 3tCLCL-15 -- -- 3tCLCL-20 0 -- -- tCLCL-5 -- 5tCLCL-20 -- 10 6tCLCL-20 -- 6tCLCL-20 -- -- 4tCLCL-10 0 -- -- 2tCLCL-5 -- 7tCLCL-10 -- 8tCLCL-10 3tCLCL-20 3tCLCL+20 4tCLCL-20 -- tCLCL-15 -- tCLCL-10 -- -- 0 tCLCL-15 tCLCL+15
Symbol 1/tCLCL tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tAVIV tPLAZ tRLRH tWLWH tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tQVWX tWHQX tRLAZ tWHLH
Parameter Oscillator frequency ALE pulse width Address valid to ALE low Address hold after ALE low ALE low to valid instr in ALE low to PSEN low PSEN pulse width PSEN low to valid instr in Input instr hold after PSEN Input instr float after PSEN Address to valid instr in PSEN low to address float RD pulse width WR pulse width RD low to valid data in Data hold after RD Data float after RD ALE low to valid data in Address to valid data in ALE low to RD or WR low Address to RD or WR low Data valid to WR transition Data hold after WR RD low to address float RD or WR high to ALE high
Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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SERIAL PORT TIMING: SHIFT REGISTER MODE
24 MHz Clock Min Max 490 406 73 0 -- 510 -- -- -- 417 40 MHz Clock Min Max 290 310 240 -- 40 0 -- -- -- 250 Variable Oscillator (3.5-40 MHz) Min Max 12tCLCL-10 10tCLCL-10 2tCLCL-10 0 -- 12tCLCL+10 -- -- -- 10tCLCL
Symbol tXLXL tQVXH tXHQX tXHDX tXHDV
Parameter Serial port clock cycle time Output data setup to clock rising edge Output data hold after clock rising edge Input data hold after clock rising edge Clock rising edge to input data valid
Unit ns ns ns ns ns
EXTERNAL CLOCK DRIVE CHARACTERISTICS
Symbol 1/tCLCL tCHCX tCLCX tCLCH tCHCL Parameter Oscillator Frequency High time Low time Rise time Fall time Min 3.5 10 10 -- -- Max 40 -- -- 10 10 Unit MHz ns ns ns ns
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Flash Program/Erase and Verification & Test Mode Characteristics Symbol Vpph Vppl Ipph Ippl tWSCV tCVQV tAVQV tCVPL tSHPL tAVPL tDVPL tPLBL tBLCX tBLAX tBLPH tBLDX tBLBH tBHSL tAXQX tCXQX tBLBHE tBLBHE1 tBLBHE2 tBLBHE3 tBLBHE4 Parameter Programming and Erase Enable Voltage Programming and Erase Enable Voltage Programming and Erase Enable Current while VPP=Vpph Programming and Erase Enable Current while VPP=Vppl Power Setup to Command Setup Low Command Valid to Data Output Valid Address Valid to Data Output Valid Command Valid to PROG Low VPP Setup to PROG Low Address Setup to PROG Low Data Setup to PROG Low PROG Low to Busy Low Command Hold after Busy Low Address Hold after Busy Low Busy Low to PROG high Data Hold after Busy Low Busy Low to Busy High VPP Hold after Busy High Output Hold after Address Release Output Hold after Command Release Busy Time while Chip Erase Busy Time while Block 1 Erase (IC89E54) Busy Time while Block 1 Erase (IC89E58) Busy Time while Block 1 Erase (IC89E64) Busy Time while Block 2 Erase (IC89E64) Min 11.5 4.5 10 30 30 30 30 1 30 30 30 30 15 1 0 0 Max 12.5 6.0 2.0 1.0 60 60 10 480 4.5 1.2 2.4 4.0 0.7 Unit V V mA mA ms ns ns ns ns ns ns us ns ns ns us us us ns ns Sec Sec Sec Sec Sec
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TIMING WAVEFORMS
tLHLL
ALE
tLLPL tAVLL tPLPH tPLIV tPLAZ tPXIZ
A7-A0
PSEN
tLLAX tPXIX
INSTR IN
PORT 0
A7-A0
tLLIV tAVIV
PORT 2
A15-A8
A15-A8
Figure 19. External Program Memory Read Cycle
ALE
tWHLH
PSEN
tLLDV tLLWL tAVLL tRLAZ tLLAX
tRLRH tRHDZ tRHDX
DATA IN A7-A0 FROM PCL INSTR IN
RD PORT 0
tRLDV
A7-A0 FROM RI OR DPL
tAVWL tAVDV
PORT 2
A15-A8 FROM DPH
A15-A8 FROM PCH
Figure 20. External Data Memory Read Cycle
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ALE
tWHLH
PSEN
tLLWL tWLWH tWHQX
A7-A0 FROM PCL INSTR IN
WR PORT 0
tAVLL tLLAX
A7-A0 FROM RI OR DPL
tQVWX
DATA OUT
tAVWL
PORT 2
A15-A8 FROM DPH
A15-A8 FROM PCH
Figure 21. External Data Memory Write Cycle
INSTRUCTION
0
1
2
3
4
5
6
7
8
ALE
tXLXL
CLOCK
tQVXH tXHQX 0 tXHDV 1 2 tXHDX
VALID
DATAOUT DATAIN
3
4
5
6
7
SET TI
VALID
VALID
VALID
VALID
VALID
VALID
VALID SET RI
Figure 22. Shift Register Mode Timing Waveform
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P3[7:6] P2[7:6]
tCVQV
00H
P3[3:2] P2[5:0] P1[7:0] P0[7-0]
30H
31H
32H
tAVQV
D5H
tAVQV
tAVQV
05H/FFH
04H/08H/10H
VPP
tWSCV
PROG VCC
Figure 23. Read Signature bytes Timing(Arming Command)
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P3[7:6] P2[7:6] P3[3:2] P2[5:0] P1[7:0] PROG
tDVPL
0EH(1)
0CH/0DH(2)
tCVPL
Valid Address(3)
tBLCX
tSLCV tCQCV
tCXQX
Valid Address(3)
tAVPL tBLPH
tBLAX
tAVQV
tAXQX
tBLDX
Valid Data(4) Valid Data
P0[7-0] P3.4(BUSY)
tSHPL
tPLBL
tBLBH tBHSL
VPP
Figure 24. Programming Timing
Note: 1. 0EH is for code memory programming . In lock bits programming, 0FH, 03H, 05H respect to lock bit 1, 2, 3. 2. 0CH is for code memory verification and 0DH is for concurrent memory verification. 09H is for Lock bits verification. 3. Address don't care while lock bits' programming or verification. 4. Data don't care while lock bits' programming.
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P3[7:6] P2[7:6] P3[3:2] P2[5:0] P1[7:0]
tCVPL
01H/02H/04H(1)
0CH/0DH(2)
tBLCX
tSLCV tCQCV
tCXQX
Valid Address(3)
tBLPH
tAVQV
tAXQX
PROG
P0[7-0]
tPLBL
Valid Data
P3.4(BUSY)
tSHPL
tBLBHE tBLBHEn tBHSL
VPP
Figure 25. Erasing Timing
Note: 1. 01H/02H/04H are for code Chip Erase/Block 1 Erase/Block2 Erase. 2. 0CH is for code memory verification. 09H is for Lock bits verification.
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tSLSH
1st stage test mode enable
2rd stage test mode enable
P2.6
tCVSL tPHCH
89H 59H 89H 59H
P0[7-0]
Figure 26. Test Mode Entering Timing Note: 1. EA, PROG, P3.7, P2.7 are high level; P3.6 is lower level.
tCLCX
Vcc -- 0.5V 0.45V
0.7Vcc 0.2Vcc -- 0.1
tCHCX
tCHCL tCLCL
tCLCH
Figure 27. External Clock Drive Waveform
Vcc - 0.5V 0.45V
0.2Vcc + 0.9V 0.2Vcc - 0.1V
Figure 28. AC Test Point Note: 1.AC inputs during testing are driven at Vcc-0.5v for logic "1" and 0.45V for logic "0". Timing measurements are made at Vih min for logic "1" and max for logic "0".
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ORDERING INFORMATION Commercial Range: 0C to +70C
Speed 12 MHz Order Part Number IC89E54/58/64-12PL IC89E54/58/64-12W IC89E54/58/64-12PQ IC89E54/58/64-24PL IC89E54/58/64-24W IC89E54/58/64-24PQ IC89E54/58/64-40PL IC89E54/58/64-40W IC89E54/58/64-40PQ Package PLCC 600mil DIP PQFP PLCC 600mil DIP PQFP PLCC 600mil DIP PQFP
24 MHz
40 MHz
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HEADQUARTER: NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK, HSIN-CHU, TAIWAN, R.O.C. TEL: 886-3-5780333 Fax: 886-3-5783000 BRANCH OFFICE: 7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD, HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C. TEL: 886-2-26962140 FAX: 886-2-26962252 http://www.icsi.com.tw
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